Artificial Intelligence Conference San Francisco 46/114

Artificial Intelligence Conference San Francisco 46/114


Bill Jenkins
Sr. Product Line Specialist , Intel

Bill Jenkins graduated with a Masters in Electrical Engineering and MBA from the University of Massachusetts Lowell, specializing in computer engineering and signal processing. He has worked in a variety of government and defense research and development companies specializing in signal and image processing using CPUs, GPUs and FPGAs. He joined Intel in 2011 as an application engineer and has since moved into a marketing, planning and strategy role.

Sessions

1:45pm–2:25pm Tuesday, September 19, 2017
Accelerating Deep Learning
Location: Franciscan CD
Bill Jenkins (Intel)
Intel has developed a Deep Learning Accelerator Library that offers a variety of primitives and architectures highly optimized for the FPGA and allowing seamless integration into the Intel ecosystem. FPGAs offer deterministic low latency, highly efficient implementations with various levels of precision from 32-bit down to binary due to its customizable architecture.​
11:55am–12:35pm Wednesday, September 20, 2017
Meet the Expert with Bill Jenkins (Intel)
Location: Table 1
Bill Jenkins (Intel)
Implementation of neural networks using FPGAs, controlling the data path for lower latency with FPGAs, improved System performance with neural networks on FPGAs, abstracting away FPGA design with the FPGA DLA Library